EtherCAT business

Development of KSJ EtherCAT communication system started in 2013, and both of hardware and software were designed / developed by ourselves to build our original master stack and slave stack. We can provide "EtherCAT master board with original master stack" which is special in the world.

Our master stack is different from other master stack vendors in terms of FPGA-based design for both master and slave. FPGA based master stack can realize high-speed periodic and high-precision transmission frame timing (veru low jitter). Those features are very important for high-spec and real-time control system.

About price, we manufactures the boards equipped with our own master stack, we have great strengths not only in price, but in product reliability. If any problem found, you can easily resolve the route cause.

KSJ products are also introduced on EtherCAT Technology Group website.　 Products on ETG>

FPGA based EtherCAT board (master / slave)

Achieved high specifications

・Master support function
"ETG.1500 class B compliant", "DC function", "Cable Redundancy", "FoE"
・Measured value of periodic time / transmission jitter
32 bit data × 1 slave system：　8 μsec (Jitter ≒ 30nsec)
40 Byte data ×5 slaves system：　40 μsec (Jitter ≒ 30nsec)

Block Diagram of master stack

High performance & cheap price!

・When supplying the board, master stack fee can be free. it enable very cheap price considering hardware and license.
(* Equipped with our developed master stack)
(* For FPGA slaves, Beckhoff IP core fee is required separately)
・When using our standard master / slave board "LZ202",
Expansion connectors make it easy to add the features / interfaces you need.
・Compatible with both Xilinx FPGA and Intel FPGA
・Available: Zynq7000 series board, Ultrascale Zynq series board

KSJ EtherCAT configuration tool

PC tool of EtherCAT configuration by connecting to KSJ master board.

Branch controller (slave stack & master stack)

FPGA-based EtherCAT master & slave installed at the same time

ESI generation tool introduction

What is an ESI file? -Building hurdles-

・Abbreviation for EtherCAT Slave Information. Slave device function and setting information.
(Product information, profiles, objects, process data, synchronization, sink manager settings, etc.)

・Must be generated according to standards and difficult to create without sufficient knowledge of EtherCAT

・Preparing C code linked to the ESI file contents for the firmware is a very laborious task.

Features of KSJ ESI generation tool

・ Three formats of files can be generated

・ Prepare GUI from the developer's point of view

CC-link IE TSN product introduction (certification test in progress)

1-axis stepping motor driver

Motion control core, NPM pulse control LSI: PCL6115 installed
3.0A / phase (max), current up during acceleration / deceleration, microstep 1/32 division,
Applicable motor: 2-phase bipolar stepping motor
Control method: Bipolar constant current drive
Excitation method: microstep control (1/1, 1/2, 1/4, 1/8, 1/16, 1/32)

For details, please see the website of Nippon Pulse Motor Corporation, the distributor. CC-link IE TSN
remote board >

History of EtherCAT development (including CC-link IE TSN)

2013	・Focusing on EtherCAT technology, started developing EtherCAT master / slave for embedding. ・Developed Lic-Z board for EtherCAT master evaluation with Xilinx Zynq SoC
2014	・Developed a original master stack that realizes EtherCAT Class B, DC function, and long-term function on ARM CPU. ・Beckhoff EtherCAT controller ET1100 + microcontroller configuration realizes EtherCAT slave
2015	・Developed EtherCAT master evaluation board LZ200 with high performance and compact design
2016	・Realized EtherCAT slave using TI AM3357 Sitara microprocessor
2017	・Started porting EtherCAT master function from ARM CPU to FPGA, and developed FPGA EtherCAT master that realizes very high speed periodic communication and low jitter by Xilinx Microblaze and original IP core. ・Developed FPGA EtherCAT master IP that can set the initial environment of EtherCAT master with ARM CPU of Xilinx Zynq ・ Developed LZ201 board for FPGA-based EtherCAT master evaluation ・Using Beckhoff IP core ET1815 / ET1816, EtherCAT slave on FPGA had been realized.
2018	・Port FPGA-based EtherCAT master to Intel Cyclone V FPGA ・Developed EtherCAT slave using Infineon XMC4300 and started motion control development ・Started developing EtherCAT slave stack FPGA IP core for Beckhoff IP core ・Developed a system that can support extremely high-speed periodic communication and high-precision synchronization using "Beckhoff IP core + KSJ slave IP core"
2021	・Started development of CC-Link-IE-TSN stepping motor driver as a remote station

Examples of Development Achievements

System	Outline	Detail
Mass flow controller for semiconductor manufacturing device	Slave： ET1100+RENESAS RX micro-processor	Control board for gas flow of semiconductor manufacturing device
Ultra-fast analog data logging system	Master： KSJ master board LZ200 series Slave： ET1100 + NXP micro-processor	Data of 3 axis accelerators (24bit×3 axis) in the building are collected by 100usec cyclic communication. Measured resonance frequency of building.
Multi axis stepping driver unit (EtherCAT interface board)	Slave： ET1100 + NXP micro-processor	Motor control unit can control 16 axis stepping motors. Synchrotron radiation facility "Spring8" uses this unit.
Tester for gas leaking	Master： KSJ master board LZ202	Enable to detect the leaking of gas from IC components or the package of medicine. Due to the merit of system cost, replaced from PLC system. Connected slave number：10 - 20 pcs
Industrial textile equipment (EtherCAT masterstack IP core)	Master： Works on Intel FPGA CycloneV KSJ Master stack IPcore was provided	As EtherCAT slave, multiple I/O unit and motors are connected to this system. 100 μsec cyclic communication is achieved.
Servo motor controller device for press machine (EtherCAT interface board)	Master： Board is equipped with Zynq7014s Slave： Board is equipped with Zynq7007s (Beckhoff slave IPcore is used)	This system is structured by 2 layers of EtherCAT line. At maximun, this system is composed by 5 master board, and 40 slave boards, with 100usec cyclic synchronized communication.
Stepping motor driver board (1 axis type / 4 axis type)	Slave： Infineon XMC4800 micro processor	250 usec cyclic communitation CiA402 motion profile Compliant
Valve controller for semiconductor manufacturing device	Master： KSJ master board LZ202 Slave： Infineon XMC4800 micro processor	CiA402 motion profile Compliant
Motor drive unit for semiconductor manufacturing device EtherCAT master stack IP core	Master： KSJ EtherCAT master stack working on ARM CPU	During 250 μsec cyclic communication, 8 motor drivers is controlled simultaniously.
Backplane system for Railroad vehicle	Master：KSJ Master stack IP core for Zynq ultrascale+ MPSoC Slave：KSJ Slave stack IP core by coding only on HDL	Slave does not have the processing unit for EtherCAT, all sequence is implemented by HDL code This system is going to acquire the certification of Functional Safety at SIL level.
Power transmission equipment for Railway system	Slave： KSJ master board LZ202	Slave is directed how to control by EtherCAT master. In FPGA logic area, PID current feedback control is implemented to excite coils.