Products
 
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Products

KSJ EtherCAT System

  • EtherCAT Master board
  • - Xilinx Zynq SoC
  • - 1GB DDR3, 32MB QSPI, microSD slot, USB UART
  • - 100Mb Ethernet x 2 for redundant EtherCAT
  • - 1Gb Ethernet, Expansion port for various kinds of I/O

  • EtherCAT Slave board
  • - Beckhoff ET1100 -Renesas R-IN32M3
  • - TexasInstruments Sitara etc.

Announcing Partnership between KSJ and RADIC
EtherCAT Logo
LZ200_01

LZ200_02 LZ200_03 LZ200_07


Self-developed EtherCAT Master, Slave boards and software
(Also ported proven EtherCAT Master software in market developed by koenig-pa GmbH from Germany)

What is EtherCAT?

EtherCAT is open Ethernet-based fieldbus network developed by Beckhoff, Germany. Fieldbus industry was looking for low data loss, high speed and real-time network with large quantities of I/O. In EtherCAT network there is no polling and handshake concept. EtherCAT frame is flying from Master to each Slave sequentially and return back to Master. Fast communication speed is realized by the processing of EtherCAT frame on the fly by each Slave.


EtherCAT Diagram



[Data size]
Maximum EtherCAT frame size is 1486 byte. This means one EtherCAT frame can control 12,000 digital I/O.

[Frame cycle]
Two kind of software is available on our Master board.
・Self-developed software by KSJ (FreeRTOS)
・koenig-pa(KPA) software (Xenomai RTOS)
Shortest cycle time of self-developed software by KSJ is 27us.
Shortest cycle time of KPA software which is running on Xenomai RTOS(Linux based real-time OS) is about 100us.
Much faster software from KPA will be announced soon.

[Synchronization]
1us synchronization between slaves is possible by DC(Distributed Clock) function of EtherCAT.


   

[KSJ EtherCAT Master Feature]

Compare between LZ200(EtherCAT Master) and Commercial PC EtherCAT Master


[Motive of developing EtherCAT board]
・PC hardware architecture is not designed for real-time systems, meaning real-time OS is difficult to run on PC environment.

・Almost all real-time OS on PC is running with Windows or other non-real-time OS. Thereby, CPU and other hardware is occupied frequently by Windows or other non-real-time OS and CPU and other hardware time for primary controlling process will be decreased.

・LZ200 board is especially designed for real-time and redundant EtherCAT system and PC is assumed for user interface usage. Security measure function will enable the possibility of independent and safe internet connection of LZ200 based control system without PC. LZ200 based EtherCAT system is more stable than PC based EtherCAT system by reason of independence of controlling part and convenient for changing system specification. (=low cost development)

[Why using Zynq?]
・Main essential condition of high performance EtherCAT system is that high speed calculation on Master side.

・Zynq which is used in LZ200 board is organized by “ARM Cortex-A9 DualCore CPU” and “FPGA”. If we use Zynq for EtherCAT master then “sequential parts like control sequence and frame send timing are executed by CPU” and “calculations which need computation power are executed by FPGA” organization is easy to achieve.

・Xilinx Vivado HLS, Xilinx SDSoC tools that generate FPGA hardware circuits from C/C++ code is available For Zynq SoC. Development time of FPGA used system will be short from this reason.


   

EtherCAT Master [Hardware specification]

Table. LZ200 board hardware spec
CPU* ARM Cortex-A9 Dual Core 666~866MHz
28k~85k FPGA logic cell
(Xilinx Zynq-7010/Zynq-7020)
Memory DDR3 SDRAM 1GB 1066Mbps
(2x512MB)
Flash memory QSPI NOR 32MB
(2x16MB)
EtherCAT 100Mbps Ethernet 2 port, RJ45 connector
Ethernet 1Gbps Ethernet 1 port, RJ45 connector
SD card microSD card slot
(SDHC, SDHS)
USB UART Max 1Mbps, miniUSB connector
I/O 80 pin expansion connector for FPGA
Power DC 24V
Size 130x80mm
Operation temperature 0 to 50℃
Other RoHS

EtherCAT Master [Master stack, development environment]

We developed our original software and at the same time KPA software is ported to our board.

Table. LZ200 board software spec
Zynq SoC development environment Xilinx ISE 14.7/Vivado 2015.4
Software development environment Xilinx SDK 14.7/2015.4
Available OS, EtherCAT Master software 1. Xenomai(RTOS)
 KPA EtherCAT Master Stack
 KPA EtherCAT Studio
2. FreeRTOS(RTOS)
 KSJ EtherCAT Master Stack
Available drivers Flash memory, SD card, other peripheral drivers of Xenomai, FreeRTOS


   

[Security of EtherCAT Master]

Security of EtherCAT Master LZ200


[Security] (option)
・ARM TrustZone technology is implemented in Zynq. This technology make it possible to keep internal security by predefining the area where is accessible from outside world. ARM TrustZone technology allows to access all Zynq area by secure software and restrict accessible area by non-secure software.

More information about ARM TrustZone technology (refer to above figure).
・CPU Core 2 software is communicating by TCP/IP stack. If CPU Core 2 is attacked by outside world, the attack influence is restricted only in CPU Core 2 and internal hardware and CPU Core 1 software is keep safe.
・CPU Core 1 is secured and communicated to outside world only by safe method.

・The communication between LZ200 and outside of the EtherCAT System is secured by AES encoding.
Generally speaking, Security function needs much logic volume, and makes original system’s performance runs worse. Fortunately, LZ200 with FPGA can avoid this negative factor. FPGA area can deal with security function very fast, and can contribute not to less original device performance.
It is true that user FPGA area will decrease when Security function is equipped, but we can chose the different size of FPGA logic cells. Therefore our customers don’t need worried about the shortness of FPGA logic cell area.

・It is possible to provide LZ200 EtherCAT Master board with security measure. Thereby, LZ200 EtherCAT Master board connect directly to cloud(by internet or intranet) without PC. Nowadays IoT(Internet of Things) importance is expected more and more and we think our IoT solution for EtherCAT would be innovative.

[Reverse engineering countermeasure] (option)
・For prevention leakage of algorithm, software or intellectual product in user area of Master board and software in Slave side, we will provide system that encode and decode Slave side software using encrypted EtherCAT communication between Master and Slave by SSL technology.

・Same as pre-encrypt Master software and decrypt it only by permitted PC using security technology above. This system fulfill the prevention leakage of intellectual property and security at the same time.

・In conclusion, we can provide the EtherCAT system which satisfy not only “Security function” but also “Reverse engineering countermeasure”. And we believe our system is one of most secured EtherCAT system in the world.


   

KPA(koenig-pa GmbH) Master Stack

KPA is a German company which specialized in EtherCAT Master Stack since many years ago. The EtherCAT Master Stack was designed to fulfill the following requirements.

・Specific optimization to run on embedded real-time operating systems
・High performance, minimum CPU time
・Small footprint
・OS independence as far as possible
・Modular architecture
・Intel and Motorola and ARM platforms support
・Development by using the EtherCAT specification only
・Implementation in ANSI “C” language. The source code of the EtherCAT Master Stack can be easily ported to other operating systems by means of “C”

KPA Master Stack classes
The following KPA Master Stack software packages are available.

1) Basic (ETG1500 Class B)
・Support of all commands and EtherCAT frames
・Support of ESM (EtherCAT State Machine)
・Checking of network or slave errors
・Cyclic process data exchange
・Online scanning
・Network configuration taken from ENI(EtherCAT Network Information File)
・Polling of Mailbox State of slave
・Mailbox transfer
・CoE (CAN application protocol over EtherCAT)
・Master side Slave to Slave communication

In extension to the requested features stated inside ETG.1500
・Adjustable scan rate for each SM
・Multiple Master instances
・Live charts and snapshots of single objects
・Station Alias Addressing
・Write access to EEPROM
・Distributed Clocks-time distribution
・Statistics gathered from NIC and Master
・CoE SDO Info Service
2) Standard in addition to Basic version (ETG1500 Class A)
・DC (Distributed Clocks)
synchronization of master and slaves with continuous delay compensation
・SoE (Servo Drive Profile over EtherCAT)
・EoE (Ethernet over EtherCAT)
・FoE (File Access over EtherCAT)
・VoE (Vendor over EtherCAT)


3) Feature Packs (added to Standard or Basic)
・Hot Connect
・Cable Redundancy
・TCP or UDP/IP Mailbox Gateway for configuring devices via EtherCAT
・Other extension features

Components
KPA EtherCAT Master Stack can be divided into Several logical parts

・API
・Process Image
・Mailbox implementation
・Master threads
・Frame scheduler
・OS abstraction layer
KPA Master Stack


   

EtherCAT Master block diagram

EtherCAT Master block diagram


EtherCAT Slave block diagram

EtherCAT Slave can be provided for each customer needs. (Able to develop using controller IC, Microprocessor, FPGA which supports EtherCAT standard)

We can develop and provide standard slave consists from “EtherCAT communication interface board” and “User circuit”. This design enables us easy to develop and provide flexible EtherCAT slave from board that is used in existing system.

Here is one example of slave block diagram.

EtherCAT Slave block diagram


EtherCAT® is registered trademark and patented technology, licensed by Beckhoff Automation GmbH, Germany.